In recent years, a CMOS image sensor has attracted attention as a solid-state image pickup element (image sensor) as an alternative to a CCD.
The reason for this is because a dedicated process is required for manufacture of CCD pixels, and a plurality of power source voltages are required for an operation of the CCD, and moreover the CCD needs to be operated based on a combination of a plurality of peripheral ICs.
Also, the reason for this is that the CMOS image sensor overcomes various kinds of problems that in the case of such a CCD, the system becomes very complicated, and so forth.
The same manufacture process as that for a general CMOS type integrated circuit can be used for manufacture of the CMOS image sensor. In addition, the CMOS image sensor can be driven by a single power source. Moreover, an analog circuit and a logical circuit each manufactured by using a CMOS process can be provided in the same chip in a mixed manner.
For this reason, the CMOS image sensor has a plurality of large merits that the number of peripheral ICs can be reduced, and so forth.
A 1 channel (ch) output using a FD amplifier having the Floating Diffusion layer (FD: Floating Diffusion) is the mainstream in an output circuit of the CCD.
On the other hand, the CMOS image sensor has the FD amplifier every pixel. Such a column parallel output type CMOS image sensor that one row lying in a pixel array is selected, and data in the one row thus selected is simultaneously read out in a column direction is mainstream in an output of the CMOS image sensor.
The reason for this is because a sufficient drive ability is hardly obtained with the FD amplifier disposed within the pixel, and thus a data rate needs to be reduced, so that the parallel processing is advantageous.
Hereinafter, a general CMOS image sensor will be described.
In the CMOS image sensor, firstly, a reset voltage (Pre-charge phase: hereinafter referred to as a P phase) is read out, and thereafter, an addition voltage (Data phase: hereinafter referred to as a D phase) obtained by adding the reset voltage and a signal voltage to each other is read out, thereby outputting a signal obtained by subtracting the reset voltage from the addition voltage.
In the CMOS image sensor, such Correlated Double Sampling (CDS: Correlated Double Sampling) is generally carried out (for example, refer to a Patent Document 1).
FIG. 1 is a diagram showing an example of a pixel, of a CMOS image sensor, composed of four transistors.
This pixel 1 has a photoelectric conversion element 11, for example, composed of a photodiode. Also, the pixel 1 has the four transistors of a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15 as active elements for the one photoelectric conversion element 11.
The photoelectric conversion element 11 photoelectrically converts an incident light into an amount of electric charges (electrons in this case) corresponding to a light quantity of the incident light.
The transfer transistor 12 is connected between the photoelectric conversion element 11 and a Floating Diffusion FD (Floating Difusion). A drive signal TG is supplied to a gate (transfer gate) of the transfer transistor 12 through a transfer control line LTx. As a result, the transfer transistor 12 transfers the electrons obtained through the photoelectric conversion in the photoelectric conversion element 11 to the floating diffusion FD.
The reset transistor 13 is connected between a power source line LVDD and the floating diffusion FD. A reset signal RST is supplied to a gate of the reset transistor 13 through a reset control line LRST. As a result, the reset transistor 13 resets a potential at the floating diffusion FD at a potential of the power source line LVDD.
A gate of the amplification transistor 14 is connected to the floating diffusion FD. The amplification transistor 14 is connected to a signal line 16 through the selection transistor 15, thereby composing a source follower together with a constant current source provided outside the pixel portion.
Also, an address signal (select signal) SEL is supplied to a gate of the selection transistor 15 through a selection control line LSEL, thereby turning ON the selection transistor 15.
When the selection transistor 15 is turned ON, the amplification transistor 14 amplifies the potential at the floating diffusion FD, thereby outputting a voltage corresponding to the potential thus amplified to the signal line 16. Voltages outputted from the respective pixels are outputted to a column circuit (column processing circuit) through the respective signal lines 16.
A reset operation of the pixel is such that the transfer transistor 12 is turned ON for the electric charges accumulated in the photoelectric conversion element 11, and thus the electric charges accumulated in the photoelectric conversion element 11 are transferred to the floating diffusion FD to be discharged.
At this time, the floating diffusion FD turns ON the reset transistor 13 to discharge the electric charges to the power source side in advance so that the floating diffusion FD receives the electric charges accumulated in the photoelectric conversion element 11. Or, while the transfer transistor 12 is held in an ON state, the floating diffusion FD turns ON the reset transistor 13 in parallel with turn-ON of the transfer transistor 12, thereby directly discharging the electric charges to the power source in some cases.
On the other hand, in a read operation, firstly, the reset transistor 13 is turned ON to reset the floating diffusion FD. In this state, an output signal is outputted to the output signal line 16 through the selection transistor 15 turned ON. This output is referred to as a P-phase output.
Next, the transfer transistor 12 is turned ON to transfer the electric charges accumulated in the photoelectric conversion element 11 to the floating diffusion FD. An output signal obtained through the transfer of the electric charges is outputted to the output signal line 16. This output is referred to as a D-phase output.
A difference between the D-phase output and the P-phase output is obtained in an outside of the pixel circuit, and a reset noise of the floating diffusion FD is canceled, thereby obtaining an image signal.
FIG. 2 is a diagram showing an example of a general configuration of the CMOS image sensor (solid-state image pickup element) in which the pixels each shown in FIG. 1 are disposed in a two-dimensional array.
The CMOS image sensor 20 shown in FIG. 2 is composed of a pixel array portion 21 in which the pixel circuits each shown in FIG. 1 are disposed in a two-dimensional array, a row selecting circuit (either a pixel driving circuit or a vertical driving circuit) 22, and a column circuit (column processing circuit) 23.
The pixel driving circuit 22 controls turn-ON/OFF of the transfer transistor 12, the reset transistor 13, and the selection transistor 15 in each of the pixels in each of the rows.
The column circuit 23 is a circuit for receiving data in the row of the pixels read-controlled by the pixel driving circuit 22, and transferring the data to a signal processing circuit in a subsequent stage.
FIG. 3 is a diagram showing a timing chart of a pixel data reading operation in the CMOS image sensor shown in FIG. 1 and FIG. 2.
In the pixel array portion in which the pixels each shown in FIG. 1 are disposed in m rows and n columns, a change in potential VSL of the vertical signal line 16 belonging to a y-th column for a time period (a time period of 1 H) for which as shown in FIG. 3, the pixels belonging to an x-th row are selected is designated by VSLy (1≦x≦m, 1≦y≦n).
A select signal SELx for the x-th row becomes a high level, thereby selecting an x-th row. Also, when the reset signal RSTx becomes a high level, the floating diffusion FD of the pixel in the x-th row and the y-th column becomes a high level, so that the potential VSLy becomes a reset level referred to as the P phase.
After that, when a drive signal TGx becomes a high level, the electric charges within the pixel move to the floating diffusion FD, and thus the potential of the floating diffusion FD drops, so that the potential VSLy of the signal line 16 drops.
A level of the potential VSLy of the signal line 16 at that time is made to be the D phase.
A difference between the D phase and the P phase is outputted similarly to the case of the foregoing, whereby a sensor output, having less noise, in which manufacture dispersions of the VSLs are canceled is obtained.